Reply To: VHDL


A while back a student built a prototype VHDL model compiler. The VHDL model compiler selection is a placeholder for a future feature. I can try to dig up a PowerPoint presentation on the topic if that would be of further interest to you.

Are you modeling a VHDL application? I’m always interested in hearing what sort of projects BridgePoint is used for. Have you had a chance to look at the training course here on